1. Field of the Invention
The present invention relates to a clock synchronization circuit for a semiconductor memory device, and in particular to a clock synchronization circuit which can improve a jitter property by outputting a clock signal having a phase between phases of two clock signals generated in a digital delay locked loop (DLL) with a predetermined time difference by using a phase mixing unit.
2. Description of the Background Art
In general, a clock synchronization circuit such as a DLL or PLL is used as a clock-generating device for compensating for a skew between an external clock signal and data or between the external clock signal and an internal clock signal.
FIG. 1 is a block diagram illustrating a conventional clock synchronization circuit for a semiconductor memory device. Here, a linear register controlled DLL is exemplified.
The conventional clock synchronization circuit includes: a receiving unit 1 for buffering an external clock signal EXCLK; a variable delay line 2 for delaying a buffered clock signal iCLK from the receiving unit 1, and generating an internal clock signal INCLK; a delay monitor 3 for monitoring a delay time of the internal clock signal INCLK from the variable delay line 2; a phase detector 4 for comparing a phase difference between the buffered clock signal iCLK and the internal clock signal INCLK, and outputting the results SHL and SHR; and a shift register 5 for controlling the delay time of the variable delay line 2 according to the output signals SHL and SHR from the phase detector 4.
The buffered clock signal iCLK obtained by buffering the external clock signal EXCLK is delayed by the variable delay line 2 for a predetermined time, and then outputted as the internal clock signal INCLK.
The internal clock signal INCLK is inputted to the phase detector 4 through the delay monitor 3, so that the phase detector 4 judges whether the internal clock signal INCLK has a faster or slower phase than the buffered clock signal iCLK.
The phase detector 4 controls the shift register 5 so that the buffered clock signal iCLK and the internal clock signal INCLK have the same phase, and controls the variable delay line 2 to delay the buffered clock signal iCLK for a predetermined time.
FIG. 2 is a detailed circuit diagram illustrating the variable delay line 2 of the clock synchronization circuit of FIG. 1.
The variable delay line 2 includes: NAND gates ND1-NDN for selectively outputting the buffered clock signal iCLK according to output signals SL1-SLN from the shift register 5; unit delay cells DEL1-DELN connected in series for delaying the buffered clock signal iCLK selectively outputted by the NAND gates ND1-NDN; and a NAND gate NDA having its one terminal connected to receive a power voltage VCC and its other terminal connected to receive the output signal from the last unit delay cell DELN, and outputting the internal clock signal INCLK.
The unit delay cell DELN includes: a NAND gate ND1N having its one input terminal connected to receive the output signal from the previous unit delay cell DEL(Nxe2x88x921) and its other input terminal connected to receive the output signal from the NAND gate ND1; a NAND gate ND2N having its one input terminal connected to receive the power voltage VCC and its other input terminal connected to receive the output signal from the NAND gate ND1N. Here, the other unit delay cells DEL1-DEL(Nxe2x88x921) have the same constitution as the unit delay cell DELN.
The operation of the conventional clock synchronization circuit will now be explained.
When it is presumed that the second signal of the output signals SL1-SLN from the shift register 5 has a high level and the other signals SL1 and SL3-SLN have a low level in an early stage, the buffered clock signal iCLK is delayed through a delay path from the second delay cell DEL2 to the last delay cell DELN, and outputted as the internal clock signal INCLK.
Here, the phase detector 4 compares the phase of the buffered clock signal iCLK with the phase of the internal clock signal INCLK. When the phase of the buffered clock signal iCLK is faster than that of the internal clock signal INCLK, the phase detector 4 outputs the control signal SHL to shift left the shift register 5.
That is, since the second signal SL2 of the output signals SL1-SLN from the shift register 5 has a high level and the other signals SL1 and SL3-SLN have a low level in the early stage, the first signal SL1 of the output signals SL1-SLN from the shift register 5 has a high level and the other signals SL2-SLN have a low level according to the control signal SHL from the phase detector 4. Accordingly, the buffered clock signal iCLK is delayed through a delay path from the first delay cell DEL1 to the last delay cell DELN, and outputted as the internal clock signal INCLK.
Conversely, when the phase detector 4 compares the phase of the buffered clock signal iCLK with the phase of the internal clock signal INCLK, if the phase of the buffered clock signal iCLK is slower than the phase of the internal clock signal INCLK, the phase detector 4 outputs the control signal SHR to shift the shift register 5 to the right.
Since the second signal SL2 of the output signals SL1-SLN from the shift register 5 has a high level and the other signals SL1 and SL3-SLN have a low level in the early stage, the third signal SL3 of the output signals SL1-SLN from the shift register 5 has a high level and the other signals SL1, SL2 and SL4-SLN have a low level according to the control signal SHR from the phase detector 4. Therefore, the buffered clock signal iCLK is delayed through a delay path from the third delay cell DEL3 to the last delay cell DELN, and outputted as the internal clock signal INCLK.
In a conventional clock synchronization circuit for a semiconductor memory device, the variable delay line 2 has the unit delay cells DELI connected in series and each unit delay cell has serially-connected NAND gates ND11 and ND21.
Accordingly, a number of the unit delay cells DELI is increased or decreased to adjust a delay time. The minimum time unit of the delay time are the delay time of one unit delay cell DEL1. As a result, a precise delay cannot be performed in a smaller unit than the delay time of the unit delay cell DEL1.
Accordingly, it is a primary object of the present invention to improve a jitter property by adjusting a delay ratio in a clock synchronization circuit composed of a digital DLL.
Another object of the present invention is to improve operation and performance by controlling the duty cycle of an internal clock signal.
In order to achieve the above-described objects of the invention, there is provided a clock synchronization circuit for a semiconductor memory device including: a clock synchronization control means for outputting a normal delay clock signal by delaying an external clock signal for a predetermined time, and outputting an additional delay clock signal by delaying the normal delay clock signal; a phase mixing means for mixing phases of the normal delay clock signal and the additional delay clock signal from the clock synchronization control means, and outputting an internal clock signal; a control means for controlling the operation of the phase mixing means, and determining a phase of the internal clock signal; a shift register for controlling a delay time of the clock synchronization means; and a phase detecting means for comparing a phase of the external clock signal with a phase of the internal clock signal, and controlling the shift register to equalize the phases of the external clock signal and the internal clock signal.